A typical processing system with video/graphics display capability includes a central processing unit (CPU), a display controller coupled to the CPU by a CPU local bus (directly and/or through core logic), a system memory coupled to the CPU local bus through core logic, a frame buffer memory coupled to the display controller via a peripheral local bus (e.g., PCI bus), peripheral circuitry (e.g., clock drivers and signal converters, display driver circuitry), and a display unit.
The CPU is the system master and generally provides overall system control in conjunction with the software operating system. Among other things, the CPU communicates with the system memory, holding instructions and data necessary for program execution, normally through core logic. Typically, the core logic is two to seven chips, with one or more chips being "address and system controller intensive" and one or more other chips being "data path intensive." The CPU also, in response to user commands and program instructions, controls the contents of the graphics images to be displayed on the display unit by the display controller.
The display controller, which may be, for example, a video graphics architecture (VGA) controller, generally interfaces the CPU and the display driver circuitry, manages the exchange of graphics and/or video data between the frame buffer and the CPU and the display during display data update and screen refresh operations, controls frame buffer memory operations, and performs additional basic processing on the subject graphics or video data. For example, the display controller may also include the capability of performing basic operations such as line draws and polygon fills. The display controller is for the most part a slave to the CPU.
In order to enhance system performance, it may be able to select the type of accesses (i.e. random, page or serial) to a given memory resource in order to optimize the execution of given processing operations. For example, graphics operations, such as line draws, often require a combination of both page mode and random accesses to the frame buffer and/or system memory. In contrast, during display refresh (which normally consumes 70% of the processing time of the display controller), a serial access may be the most efficient. In sum, because of the nature of instruction execution, certain types of memory accesses are better suited to the performance of certain processing operations.
However, access mode changes cannot be efficiently implemented with currently available memories devices and architectures. This is particularly true with regards to system memories, to which most of the real-time accesses are made during data processing. The typical system memory is constructed of single in-line memory modules (SIMMs). SIMMs normally include one or more dynamic random access memory devices (DRAMs) which are controlled by two clocks: a row address strobe (RAS) and a column address strobe (CAS). SIMMs operate only during one mode during a given RAS active cycle, normally the period when RAS is held at a logic low. Thus, the change from one mode to another, for example from random mode to page mode, requires a delay until the next active RAS cycle is initiated. Similar limitations are found with the use of single packaged DRAMs used to construct such memory resources as the display frame buffer.
In sum, no memory device is currently available in which given percentage of each RAS cycle may be used for random accesses, another percentage for page mode accesses and a further percentage for serial accesses. As discussed above, the ability to optimize processing operations by optimizing the type of memory access supporting those operations is highly advantageous. Thus, the need has arisen for circuits, systems and methods which allow for the efficient changing of modes in a memory device. In particular, such circuits, systems and methods should allow for multiple access modes to be utilized in a single RAS cycle.